Yazar "Ramazanoglu, Semih" seçeneğine göre listele

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    Design and Comparison of Low Power Pulse Combining IR-UWB Transmitters in 180nm CMOS
    (IEEE, 2019) Ramazanoglu, Semih; Dundar, Gunhan; Batur, Okan Zafer
    This paper presents design and comparison of low power pulse shaping methods for achieving low energy per pulse (EPP), Impulse Radio Ultra-Wideband (IR-UWB) transmitter. The proposed transmitters are composed of all digital single pulse generator, multiple delay lines, a pulse combination circuit, and pulse shaping stages with a pulse shaping capacitor and wire-bond inductor at the output. The generated mono pulse width and the consecutive mono pulse positions are determined by the delay lines. The proposed transmitter architectures are designed in 180 nm CMOS technology, and supply voltage is 1.8V. The simulation results show that the energy required to generate the Gaussian mono-cycle, triplet, and quintuplet pulses are 10.5 pJ, 22.15 pJ, and 36.5 pJ respectively at 200 MHz pulse repetition frequency (PRF) without band pass filter (BPF). The required energies utilizing a BPF to generate output signals are 17.5 pJ, 31.5 pJ, and 46 pJ respectively.
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    Switched Capacitor Variable Delay Line
    (IEEE, 2018) Ramazanoglu, Semih; Batur, Okan Zafer
    In this paper, we present a new configurable switched capacitor loading technique to achieve a shunt capacitor variable delay line with reduced capacitor area. Proposed delay line employs only two configurable and switchable capacitors to achieve the required delay value. Thermometer coded capacitors are utilized for linear and nondecreasing delay. The proposed architecture has high linearity figures with 0,0104 DNL & 0,0618 INL. The delay steps can be configured with 100 pS/step. Maximum delay range of the 10 cascaded delay cells is 10 nS. The delay cells can be activated separately to increase the control over the required delay range. The maximum operating frequency of a single delay cell is 90 MHz. The delay line architecture is designed in UMC 180 nm CMOS technology and simulation results are presented. The circuit operates with 1.8 V supply and the core delay cell consumes 95 mu W at 10 MHz PRF. The delay line with 10 cascaded delay cells consumes 536 mu W at 5 MHz PRF. Achieved linearity value of R-2 is 0,9999.