Switched Capacitor Variable Delay Line

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dc.authoridbatur, okan zafer/0000-0002-1585-1794|RAMAZANOGLU, SEMIH/0000-0002-1553-6567
dc.authorwosidbatur, okan zafer/W-5712-2019
dc.contributor.authorRamazanoglu, Semih
dc.contributor.authorBatur, Okan Zafer
dc.date.accessioned2024-07-18T20:47:26Z
dc.date.available2024-07-18T20:47:26Z
dc.date.issued2018
dc.departmentİstanbul Bilgi Üniversitesien_US
dc.descriptionIEEE International Symposium on Circuits and Systems (ISCAS) -- MAY 27-30, 2018 -- Florence, ITALYen_US
dc.description.abstractIn this paper, we present a new configurable switched capacitor loading technique to achieve a shunt capacitor variable delay line with reduced capacitor area. Proposed delay line employs only two configurable and switchable capacitors to achieve the required delay value. Thermometer coded capacitors are utilized for linear and nondecreasing delay. The proposed architecture has high linearity figures with 0,0104 DNL & 0,0618 INL. The delay steps can be configured with 100 pS/step. Maximum delay range of the 10 cascaded delay cells is 10 nS. The delay cells can be activated separately to increase the control over the required delay range. The maximum operating frequency of a single delay cell is 90 MHz. The delay line architecture is designed in UMC 180 nm CMOS technology and simulation results are presented. The circuit operates with 1.8 V supply and the core delay cell consumes 95 mu W at 10 MHz PRF. The delay line with 10 cascaded delay cells consumes 536 mu W at 5 MHz PRF. Achieved linearity value of R-2 is 0,9999.en_US
dc.description.sponsorshipIEEE,Politecnico Torino,Analog Devices,CADENCE,Texas Instruments,AiCTX,Springer Nat,River Publishers,Nat Electron,CASen_US
dc.description.sponsorshipScientific and Technological Research Council of Turkey (TUBITAK); Istanbul Bilgi University Research Foundation (BAF) [2017.02.009]en_US
dc.description.sponsorshipThis work was supported by The Scientific and Technological Research Council of Turkey (TUBITAK) and Istanbul Bilgi University Research Foundation (BAF) under Contract 2017.02.009. Authors would like to thank to all of the members of Microsystems Laboratory of Istanbul Bilgi University for their support.en_US
dc.identifier.doi10.1109/ISCAS.2018.8351457
dc.identifier.isbn978-1-5386-4881-0
dc.identifier.issn0271-4302
dc.identifier.scopus2-s2.0-85057085168en_US
dc.identifier.scopusqualityN/Aen_US
dc.identifier.urihttps://doi.org/10.1109/ISCAS.2018.8351457
dc.identifier.urihttps://hdl.handle.net/11411/7778
dc.identifier.wosWOS:000451218702140en_US
dc.identifier.wosqualityN/Aen_US
dc.indekslendigikaynakWeb of Scienceen_US
dc.indekslendigikaynakScopusen_US
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.relation.ispartof2018 Ieee International Symposium on Circuits and Systems (Iscas)en_US
dc.relation.publicationcategoryKonferans Öğesi - Uluslararası - Kurum Öğretim Elemanıen_US
dc.rightsinfo:eu-repo/semantics/closedAccessen_US
dc.subjectPhase-Locked Loopen_US
dc.titleSwitched Capacitor Variable Delay Lineen_US
dc.typeConference Objecten_US

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